1. Field of the Invention
The present invention is related to device characterization methods and circuits, and more particularly to array-based techniques for measuring early threshold voltage recovery.
2. Description of Related Art
As geometry and power supply voltages in very large-scale integrated circuits (VLSI) such as semiconductor memories and microprocessors are decreased, the effect of threshold voltage variation has become increasingly significant. Not only do process variation changes in threshold voltage cause variation from device-to-device, but effects such as negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) cause changes in performance that are time and stress dependent. The mechanisms behind NBTI and PBTI are not fully understood, and measurements of their effects have been limited by their time-dependent nature.
NBTI effects are seen when a negative gate voltage stress is applied to a P-channel metal-oxide semiconductor (MOS) transistor, and the effects diminish rapidly during the recovery time immediately following removal of the stress. Similarly, PBTI effects are seen in N-channel MOS devices. Therefore, in order to properly characterize NBTI/PBTI effects and gain insight thereby into the mechanisms causing NBTI/PBTI, it is desirable to measure threshold voltage not only during the application of the stress and after removal of the stress, but to characterize the threshold voltage variation during the time period between removal of the stress and recovery of the initial (non-stressed) threshold voltage.
Present measurement techniques provide threshold voltage observation in the range of 100 microseconds and later by measuring the drain current of a transistor having fixed drain and source voltages and responding to a step voltage at the gate of the transistor that transitions from the stressed condition (negative gate voltage) to an unstressed condition. The NBTI/PBTI effects are masked during the early portion of such measurements by the delays in both the operation of the transistor, i.e., delays due to the transition time of the transistor, and the test instrumentation, i.e., the delays inherent in making a current measurement. It would be desirable to eliminate as many of the measurement delays as possible. Further, current-based measurement of threshold voltage relies on a model of the drain current versus gate voltage in order to determine the actual change in threshold voltage due corresponding to the drain current changes. As a result, drain current-based NBTI/PBTI measurements are typically not reflective of the true dynamic operation of logic circuits and the transient nature of the effect of NBTI/PBTI on logic circuits. Finally, drain current-based measurements typically operate the drain-source terminals near their full on-state current level, which makes it difficult to simultaneously test a large number of devices in an array due to the high current requirement when multiple devices are turned on.
Therefore, it would be desirable to provide threshold voltage characterization that measures early effects of threshold voltage change due to NBTI and PBTI. It would further be desirable to provide such threshold voltage characterization that measures the NBTI/PBTI effect under transistor terminal conditions reflecting actual operating conditions in a logic circuit. It would further be desirable to perform such measurements in an array environment, so that multiple measurements can be performed across a die.